This invention concerns a low inductance ceramic capacitor structure having multiple capacitor plates which are terminated at a common face and more particularly, an improved structure and method of its making wherein the plate terminations are aligned and isolated by grooves in the common face.
The continuing objective of data processing equipment designers is to produce equipment having increased operating speed, reduced physical size and lower manufacturing cost.
Designers seek this objective today by attempting to pack as many circuit devices as possible into the integrated circuit chips that go to make up the equipment. By packing as many devices as possible on a chip, the designer reduces the length of interconnections needed to join the devices which tend to slow circuit operation down, thereby enabling faster operation. Additionally, by increasing the number of circuit devices per chip, the designers eliminate previously unused space with the result that the physical size of the equipment is reduced. Finally, since the manufacturing cost per chip tends to be fixed, by fitting more devices on a chip, designers are able to reduce the manufacturing cost per device i.e., less chips are required for the same number of devices.
Efforts to produce more devices per chip have resulted in the so-called very large scale integrated circuit technology (VLSI) which today represents the state of the semiconductor art. This technology is capable of producing as many as 20,000 memory units and associated circuitry on a single chip or as many as 4,000 logic units and associated circuitry on a single chip.
Unfortuantely, however, VLSI and, in fact integrated circuits generally, have not been a complete answer for designers. Because of limitations associated with semiconductor materials and integrated circuit size, it has not been possible to conveniently build in an integrated form the full range of circuit elements the designer desires. While it is relatively simple to build transistors, diodes and even resistors, it has not proven convenient to build capacitors and inductances of the values typically required.
Capacitors are a particular problem. Where capacitance of other than a very low value are desired, the dielectric material constant and plate area available in integrated circuit form make such capacitors difficult or impossible to build.
To deal with this, designers have used discrete capacitors, i.e. capacitors separate from the circuit chip, to cooperate with the chip to form the full circuit. However, to retain the advantages of integrated form, the designers have sought discrete capacitors of small size, high speed and low cost.
A particular capacitor design found to be suitable for use with VLSI circuits is described by Chance et al in his co-pending application Ser. No. 164,119, filed June 30, 1980, assigned to the assignee of this application. The Chance et al structure is of small size, high speed and low manufacturing cost. The structure is of the laminated ceramic parallel plate type, and includes multiple capacitor sections, each having a ceramic dielectric layer which has been metallized to form a capacitor plate. The structure is formed to a desired size by combining the multiple sections.
The structure has low inductance and, therefore, high speed as well as small size because the capacitor plates are exposed at a common capacitor body face and joined by means of metallic strips which act as low inductance interconnection buses. To facilitate this construction, each capacitor plate is provided with one or more tabs which are spaced in the direction of the body width. The tabs thereafter are interconnected by means of the interconnect buses. Final connection of the capacitor structure to other circuit elements, for example the VLSI chips, is accomplished by flip-chip mounting the structure on a multi-layer ceramic substrate with the use of solder balls as also described in the Chance et al patent application above noted.
To make the Chance et al structure as small as possible, the lateral spacing of the plate tabs is reduced to a minimum. For example, the plate tabs are typically 4 to 8 mils in width spaced 7 to 10 mils apart.
Unfortunately, due to the small sizes involved it is difficult to properly locate the tabs and buses to avoid undesired interaction. Additionally, due to ceramic shrinkage in curing, it is common for the plate tab location to drift, further aggravating the mis-alignment. Because of these problems, minimal size for the capacitor structures has been difficult to attain.